Description
sorthdl
sorthdl is a handy little tool for designers who might not be sure about the dependencies of their VHDL or Verilog files in a specific design. If you’re unsure which file to compile and where, this tool is here to help!
How sorthdl Works
So, here’s the deal: sorthdl takes all your RTL files as input. It then processes these files behind the scenes and gives you a nice, sorted list of files along with their correct VHDL or Verilog work library. Pretty cool, right?
Input File Requirements
To get started, you need an input file that lists all your Verilog and/or VHDL files. Just make sure there’s one file per line and no special characters like * or regular expressions in the file names.
Creating Your Input File
You can easily create this input file by redirecting the output of the 'ls' command. Just remember: no funny business with special characters like '*' or '@' in your filenames.
The Final Output
Once sorthdl processes everything on your list, it will generate a compilation script for ModelSim named 'modelsim_compile.csh'. This means you can jump right into compiling without any hassle!
Ready to Get Started?
If you're looking to streamline your design process with sorthdl, check out more details about it on SoftPas. It’s definitely worth a look!
User Reviews for sorthdl FOR MAC 1
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for sorthdl FOR MAC
sorthdl for Mac is a lifesaver for designers! It effortlessly sorts VHDL / Verilog files and generates a handy modelsim compilation script.