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FREE
License
PAID
Version
Verilog Flattener 16 FEB 2013
LatestUpdate
Last updated
OS
Language
EN
Verilog Flattener was designed as a Java-based and accessible utility that takes all the verilog RTL files along with the top verilog module name and traverses the entire hierarchy starting from the top.
It removes each of the instances by pulling that's functionality in the top module. Please note that it supports mainly the synthesizable verilog constructs.
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