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FREE
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PAID
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Verilog RTL Parser 06 APR 2013
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verilogparser is a simple, accessible and handy parser that's been developed for those who want to design their own utility around verilog RTL.
This parser has been developed in Java in order to make it platform independent. It reads RTL and populates its internal data structures.
There are APIs to extract the design information from the database, there are APIs to elaborate every element of design along with expression evaluation capabilities.
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